1. Field of the Invention
The present invention relates to high-performance memory controllers and more specifically relates to methods and structure for improved sequencing of precharge and activation commands in a high-performance SDRAM memory controller.
2. Discussion of Related Art
In present day digital electronic systems, high performance memory subsystems are comprised of a plurality of banks of memory with each bank comprising a plurality of memory chip devices. High-performance memory chip devices typically provide for burst modes of access to help optimize bandwidth utilization of the memory device by an associated master or controlling device. Generally a xe2x80x9cburstxe2x80x9d operation is one where a single read or write command may access a sequence of locations within the memory chip device in rapid succession without requiring further sequences of logic signals applied to the memory chip device to access each sequential location. Further, multiple banks of such memory chip devices may be operated in a variety of parallel fashions to overlap processing in one bank of memory with processing in other banks of memory. Such features are well-known in the art to improve performance of memory subsystems.
In general, present-day high-performance memory subsystems utilize a memory controller device between the master device intended to utilize the memory subsystem (i.e., a general purpose processor or other special-purpose processing devices) and the memory subsystem. Such a memory controller device is intended to shield the master device from details of a controlling the memory chip devices and the memory banks to achieve optimal memory subsystem performance. For example, such memory controller devices assume responsibility for controlling the memory chip devices to best utilize burst mode operations and further controlling the multiple banks of memory to permit significant overlap in processing memory operations among the plurality of banks.
A number of current high-performance memory subsystems utilize SDRAM (synchronous dynamic random access memory) memory chip devices as well as variants of such SDRAM devices that provided double data rate operations (i.e., DDR SDRAMs). As used herein, xe2x80x9cSDRAMxe2x80x9d refers to both standard SDRAM memory devices and DDR SDRAM memory devices. Features of the present invention as discussed further herein below are applicable to both types of SDRAM devices as well as other memory chip devices.
As is known in the art, industry standard specifications provide for a command structure in accessing SDRAM devices. For example, JEDEC standard JESD79 provides a standardized specification for commands used in accessing DDR SDRAM devices (published by the JEDEC Solid State Technology Association in June of 2000 and available publicly at www.jedec.org). Similar command structures are defined for access to all SDRAM devices as well as other types of memory chip devices. A memory controller device responds to memory operations requested by the master device and translates the request into appropriate SDRAM commands in an appropriate sequence to store or retrieve the requested data to or from the memory chip devices. The memory controller device therefore assumes responsibility for optimal use of available bandwidth for the memory devices.
Addressing a location (or sequence of locations) in a memory chip device involves selecting a column and a row (also referred to as a xe2x80x9cpagexe2x80x9d). The standardized command structure for accessing SDRAM devices (and other memory chip devices) requires that the desired page or row of a memory device must be open or active prior to reading or writing data from or to a memory location in that page. An xe2x80x9cactivatexe2x80x9d command is typically used to specify the page or row to be opened prior to issuance of a read or write command accessing locations within that page. Typically, the activate command also specifies which bank of a multibank memory subsystem is to be activated. An active or open page is closed or made inactive by a xe2x80x9cprechargexe2x80x9d operation. A typical sequence therefore involves closing a previously open page with a precharge command, opening a next page to be accessed with an activate command, and then issuing an appropriate read or write command to retrieve or store the desired data from or. to memory locations in the open page.
The synchronous nature of SDRAM devices generally requires that some command be present on the input signal paths of the memory chip devices at each clock pulse applied to the memory chip device. When a read or write command is issued that requests a burst of a number of sequential locations, one or more clock cycles may be applied to the memory chip device before another read or write operation is permitted. To assure that some command is applied to the input of the memory chip device, typical memory controller devices generate nop commands to fill the otherwise unused command sequences during burst cycles. Other sequences of commands also require application of nop commands during latency periods awaiting completion of an earlier issued command to the memory chip device. For example, there is typically a latency following issuance of an activate command before the specified page is open and ready for a read or write command. Such latency periods are typically filled with nop commands by memory controller devices.
It is a constant problem to improve memory bandwidth utilization to thereby improve overall system performance for an associated system. Methods and structures that improve memory subsystem bandwidth utilization are therefore desirable. In particular, it is desirable to reduce the latency between activation of a page of memory and access to the opened page.
The present invention solves the above and other problems, thereby advancing the state of useful arts, by providing methods and structure for inserting activate commands in place of nop commands generated by the memory controller device. In particular, methods and structure of the present invention determine that future read or write operations may require activation of a new page. In response to detecting a need for activation of another page in the near future, and appropriate activate command is inserted in place of a nop command in the standard sequence of commands issued to the SDRAM device.
Still more specifically, the present invention maintains a FIFO queue of activate commands pending for memory pages required by future read or write operations issued to an SDRAM memory device. The FIFO preferably has a depth equal to the number of banks in the multibank memory subsystem architecture. As future read or write operations are detected in the command stream issued to the memory controller for other banks of memory, an activate request will be queued in the FIFO for the corresponding page of the corresponding bank. As command sequences are generated by the memory controller for application to the SDRAM memory device, each nop command cycle may be replaced by an appropriate activate command for a next page to be accessed by future read or write commands sensed by the memory controller. The methods and structure of the present invention therefore help improve utilization of memory bandwidth in high-performance memory subsystems by inserting activate commands (also referred to herein as xe2x80x9chidden activatesxe2x80x9d) in advance of reading or writing of the associated open page. The required page will therefore be ready for access by an appropriate read or write command sooner than would otherwise be the case in a memory subsystem devoid of the present invention. This reduced latency between page activation and page access improves memory bandwidth utilization and hence overall system performance.
A first aspect of the invention provides a method operable in a memory controller for improving memory bandwidth utilization comprising the steps of: directing a first burst memory access command from the memory controller to a first bank of the multiple banks of memory in response to receipt of a first memory access request from a master device wherein the first burst memory access command requires multiple clock periods to complete; sensing, within thememory controller, receipt of a next memory access request from a master device during the multiple clock periods wherein the next memory access command requires access to a second bank of the multiple banks of memory; and directing an activate command from the memory controller to the second bank during the multiple clock periods to overlap operation of the activate command with the period of time.
Another aspect of the invention further provides that: the step of sensing includes the step of: queueing an activate request in an activate queue associated with the memory controller, and that the step of directing an activate command includes the step of: unqueueing the activate request from the queue to generate the activate command to be directed to the second bank.
Another aspect of the invention provides a method operable in the memory controller for improving memory bandwidth utilization comprising the steps of: receiving high level commands for burst memory operations from the master device; operating a state machine for each bank of the multiple banks to generate synchronous memory commands for the each bank in response to high level commands directed to the each bank wherein the synchronous memory commands include read burst commands, write burst commands, nop commands, activate commands and precharge commands; and sequencing the synchronous memory commands for application to the multiple banks to replace nop commands generated for a first bank with precharge and activate commands for a second bank.
Yet another aspect further provides that the step of sequencing comprises the steps of: prioritizing the synchronous memory commands generated for the each bank such that read commands and write commands are applied to corresponding bank in the order received from the master device and such that a read command or a write command for an active row of a bank takes precedence over any other synchronous memory command and such that an activate command or a precharge command for an inactive row takes precedence over a nop command and over a read command or a write command for the inactive row; selecting a command of the synchronous commands for application to a corresponding bank; and applying the command to the corresponding bank.
Still another aspect of the invention provides for a memory controller including: an activation FIFO for queueing activation requests for identified banks of the multiple banks; a command decoder coupled to the activation FIFO for decoding high level commands received from an associated controlling device and for queueing activation requests derived from the high level commands in the activation FIFO; a plurality of state machines operable to process the decoded high level command and to generate corresponding sequences of low level command cycles for application to the SDRAM memory device wherein each state machine operates on behalf of a corresponding bank of the multiple banks; an input selector coupled to the command decoder and to the activation FIFO and to the plurality of state machine to select between a decoded command from the command decoder and an activation request in the activation FIFO for application to the state machine for a bank identified in the selected decoded command or in the selected activation request; and a nop detector for detecting when a next command cycle generated by the plurality of state machines will be a nop command cycle and for generating a signal indicative of such a nop command cycle and for applying the signal to the input selector, whereby the memory controller replaces a nop command cycle with an activate command in accordance with queued activation requests in the activation FIFO.